System and method for implementing package level IP preverification for system on chip devices

ABSTRACT

A method for implementing package-level intellectual property (PLIP) preverification for system on chip (SOC) devices includes providing at least one externally connected intellectual property (IP) core with an SOC. A package generic unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein said package generic unit is pre-verified in silicon and independent of the specific packaging of the SOC. A package adaptation unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein the package adaptation unit is pre-verified in silicon and dependent upon the specific packaging of the SOC.

BACKGROUND

The present invention is generally within the field of integratedcircuit (IC) device design and verification, and, more particularly,defines a new concept: package-level intellectual property (PLIP)embodied by a system and method for implementing the PLIPpreverification for system on chip (SOC) devices. The SOC devices arevery complex IC's that integrate tens of millions or hundreds ofmillions of transistors on single silicon chip.

To expedite the development of integrated circuits, chip designerstypically combine standard cells from cell libraries. Cells may containgeometrical objects such as, for example, polygons (boundaries), paths,and other cells. Objects in the cell are assigned to “layers” of thedesign. Cells may be very simple structures that consist of a fewtransistors, or may be very complex structures that contain thousands ormillions of transistors. The cells of the latter type are commonlyreferred to as “intellectual property” (IP), which represents a higherlevel of abstraction of a standard cell. Typically, IPs are provided byan IP vendor. As is illustrated by the process flow diagram of FIG. 1,an IP vendor develops and verifies each IP separately (blocks 102, 104),with the expectation that IC layouts that employ the IP will also meetspecifications.

Practically speaking, an EP block is only viable if it takes less effortto integrate into an IC than it would to develop the block from scratch.Because IP blocks tend to be used as supplied (with no changes apartfrom those required by integration), functional verification of the IPblock just by itself is less important, and has already been done duringits development. Rather, the verification should be designed to showthat the rest of the system correctly supports the IP block, and thatits presence does not upset the other parts of the design.

Accordingly, an IC designer selects the cells or IPs it wishes to use inan IC layout to provide whatever structures or functionalities arerequired for a particular application. Each cell has one or moreconnectivity targets, which are predetermined points used to connect thepatterns in a pair of cells. After the verification of the functionaldesign of the cell selections in block 106 (e.g., synthesis by RegisterTransfer Level (RTL) simulations and translation of the RTL models to aSPICE (Simulation Program with Integrated Circuit Emphasis) netlist),the layout is submitted to a routing program (blocks 108, 110), whichconnects the target-containing patterns of the adjacent cells to formcomplete sets of patterns for each mask layer. When a designincorporates two cells adjacent to each other in an IC layout, therouter identifies the location of the connectivity target in each cell,and constructs a connecting path between the targets, comprising one ormore line segments. This connecting path is incorporated into the IClayout (block 112), so that the mask constructed from the connectedcells includes continuous circuit paths.

Subsequently, the IC layout is submitted for artwork verification atblock 114 (for example, using a program such as Calibre, by MentorGraphics of Wilsonville, Oregon). In the artwork verification process,compliance with design rules is checked. For example, the line spacingbetween each pair of adjacent lines is compared to the relevant minimumfor that line. If the line spacing is less than the minimum required forthe width of the merged line, a design rule violation is identified.Finally, cell-based IC design focuses on the package design andverification for the chip die (mechanical and electrical) as shown inblock 116, 118.

More recently, complex SOC designs include existing, preverified IPlibraries, as well as newly designed components. Depending upon the roleof the IP in the SOC, certain IPs may be completely embedded inside thechip itself (i.e., no external connections to/from the die) whilecertain other fPs are used solely for communication of the signals ofthe SOC to the outside world. In the latter case, this type of IPcontinues to be operated at higher and higher signal rates (e.g.,sub-gigabit per second to tens of gigabits per second). As such, theimplementation and integration of this type of IP into an SOC presentssignificant challenges. Unfortunately, the two general types of existingimplementable IPs (i.e., soft IP cores and hard IP cores) provide only apartial solution for IP integration and validation of complex SOCs, interms of functionality, time to market, and profit. For example,conventional soft IP blocks are only validated up through thesynthesizable RTL stage (blocks 102-104), while conventional hard IPblocks are only validated up through the GDS (Graphic Design Solutions)artwork stage (blocks 102-114).

Accordingly, it would be desirable to be able to provide an IP productthat overcomes the existing integration and validation problemsassociated with present day SOC designs, such as (for example) thoseincluding mixed signal IPs therein.

SUMMARY

A system for implementing package-level intellectual property (PLIP)preverification for system on chip (SOC) devices is presented. In anexemplary embodiment, the system includes at least one intellectualproperty (IP) core formed on an integrated circuit die, the at least oneIP core having external connections with respect to the die. A packagegeneric unit is included within the at least one IP core, the packagegeneric unit configured for providing external interface functions withrespect to the SOC, wherein the package generic unit is pre-verified insilicon and independent of the specific packaging of the SOC. A packageadaptation unit is included with the at least one IP core, the packageadaptation unit configured for providing external interface functionswith respect to the SOC, wherein said package adaptation unit ispre-verified in silicon and dependent upon the specific packaging of theSOC.

In another embodiment, a method for generating preverified,package-level intellectual property (PLIP) for system on chip (SOC)devices is presented. The method includes defining at least oneintellectual property (IP) core to be included in an SOC formed on anintegrated circuit die, the at least one IP core having externalconnections with respect to the die. A package generic unit is definedwith the at least one IP core, the package generic unit configured forproviding external interface functions with respect to the SOC, whereinsaid package generic unit is pre-verified in silicon and independent ofthe specific packaging of the SOC. A package adaptation unit is definedwith the at least one IP core, the package adaptation unit configuredfor providing external interface functions with respect to the SOC,wherein the package adaptation unit is pre-verified in silicon anddependent upon the specific packaging of the SOC.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numberedalike in the several Figures:

FIG. 1 is a schematic block diagram of an SOC design and verificationprocess;

FIG. 2 is a schematic block diagram of an exemplary SOC having one ormore vendor supplied IP cores, in addition to the customized chip logic;

FIG. 3 is a schematic block diagram of the SOC as provided within asemiconductor package;

FIG. 4 is a schematic block diagram of a novel method and structure ofan IP core that is pre-verified at a package level, in accordance withan embodiment of the invention;

FIG. 5 is a more detailed block diagram of the package generic unitincluded in the pre-verified IP core of FIG. 4; and

FIG. 6 is a more detailed block diagram of the package adaptation unitincluded in the pre-verified IP core of FIG. 4.

DETAILED DESCRIPTION

Disclosed herein is a method and system for implementing package levelintellectual property (IP) preverification for system on chip (SOC)devices. In an exemplary embodiment, a new class of IP product isdefined, and may be referred to hereinafter as a package level EP(PLIP). Under this approach, an IP block is provided and verified at thepackage level. That is, in addition to the testing and verificationprovided with conventional soft or hard EP blocks, the PLEP is alsoprovided with (for example), functional and timing verification,completed in design and confirmed in silicon, verification of productionreliability (e.g., electrostatic discharge (ESD), latchup, etc.), andverification that bonding wire impact is properly compensated for,tested and characterized in real silicon. Because the PLEP has beenpre-validated up to a package level before a user (e.g., SOC designer)acquires the same, a complete solution is provided by the EP vendor.

Structurally, the PLEP includes two main units: a package generic unitand a package adaptation unit. The package generic unit is independentof what specific package the chip is incorporated into. The packageadaptation unit is, on the other hand, package dependent and also mustbe pre-verified in silicon. Further, the package adaptation unit ismeant to address issues such signal integrity, ESD, load compensation,impedance matching, and mechanical adaptation. In one embodiment, thepackage adaptation unit may be implemented in such forms as a puremechanical adaptor, input/output (I/O) pads with matching bonding wire,or additional silicon fabrication mask layers, depending on the specificnature of the fP and the package characteristics.

Referring now to FIG. 2, there is shown a schematic block diagram of anexemplary system on chip (SOC) 200 having one or more vendor supplied EPcores 204, in addition to the customized chip logic. As is shown, theSOC is formed within an integrated circuit die 202, the area of which isdivided into subregions designated A through I in FIG. 2. In particular,regions A through H represent vendor supplied IP cores 204 (e.g., softIP cores, hard IP cores), while region I contains the customized chiplogic specific to the SOC 200. Certain IP cores may be configured so asto have no external connections with respect to the die 202, whilecertain other fP cores may have external connections with respect to thedie 202. In the example illustrated, a first group of IP cores (e.g., A,B, D, E, F, and G) include external connections while a second group ofIP cores (e.g., C, H) does not.

FIG. 3 is another schematic block diagram of the SOC 200 as providedwithin a semiconductor package 300. Region 302 depicted within the SOC200 represents one or more of the first group of IP cores havingexternal connections with respect to the chip. Such connections,generally depicted by 304, can include (for example) bond wires that areconnected between pads on the die 202 and corresponding conductorsprovided in the package 300. For an SOC that is packaged in the manneras depicted in FIG. 3, an IC provider conventionally assumes the burdensof integrating and verifying, and fine-tuning the design of the IPs intothe silicon of the die 202 and the packaging 300, particularly wheresuch IPs represent high-speed connectivity IPs of a mixed signal design.In other words, the chip designer/manufacturer and not the individual IPprovider conventionally implements the steps shown in blocks 116 and 118of FIG. 1.

Accordingly, FIG. 4 illustrates a schematic block diagram of a novelmethod and structure of an IP core 400 that is pre-verified at a packagelevel. In addition to the functional logic elements of the IP coreitself (generally depicted at 401), the PLIP 400 further includes apackage generic unit 402 and a package adaptation unit 404. In onesense, the functional “IP specific” logic portion 401 of the IP core 400is somewhat similar to a conventional IP in hardmacro form, except thatthe functional logic 401 must be pre-verified in silicon together alongwith the package generic unit 402 and package adaptation unit 404. Morespecifically, FIGS. 5 and 6 further illustrate the various majorfunctional components of each respective unit.

In particular, the package generic unit (PGU) 402 shown in FIG. 5handles all functional electrical aspects of the IP. In an exemplaryembodiment, the PGU 402 includes several major sub-blocks. First, a“Powering and Level Shifting” sub-block 502 is configured to convert theI/O signal voltage level to the proper range as defined by industrystandards (since SOC internal signal voltages are typically much lowerthan those of I/O levels). Sub-block 502 also provides various packageindependent functions related to internal power distribution of the PLIPwithin an SOC.

A “Custom Internal Interface” sub-block 504 is provided for separatingthe SOC internal control signals and the I/O signals. In addition, a“Pull up & Pull down” sub-block 506 adjusts the line voltage to a properlevel when there is no real data currently being transmitted orreceived. An “I/O Transceiver (stage I)” sub-block 508 represents thepackage independent stage of the I/O transceiver included in the IP, anda “Threshold & Enable” sub-block 510 generates control signals used byother sub-blocks of the PGU 402, such as the “I/O Transceiver (stage I)”sub-block 508 and the “Pull up & Pull down” sub-block 506.

Referring to FIG. 6, the package adaptation unit (PAU) 404 handles thepackage related aspects (electrical and mechanical) of the IP. The PAU404 also has a plurality of major sub-blocks including, for example a“Package RCL” sub-block 602 configured for modeling parameters such asresistance, capacitance, and inductance along a trace from a package pinto a pin on the SOC die. The RCL value and associated network are uniqueto the package that a particular SOC uses. A “Signal Landing” sub-block604 is a mechanical sub-block in which signals physically connectedto/from the die are routed therethrough. This may be embodied, forexample, by a flat metal area on the die for soldering a wire (wire bondpackage), or it may be a few mask layers for re-distributing signal pinson the top of the die in such way that the pins are mechanically alignedto pins on the package.

In addition, a “Powering and Power & Ground Clamps” sub-block 606 isconfigured for electrostatic discharge protection of the SOC, as well asfor package dependent aspects of power distribution to the PLIP insidean SOC (e.g., routing of power lines from a chip package, power landingcontacts on the SOC, etc.). An “Impedance Match & Line Termination”sub-block 608 minimizes signal reflection for both directions, and an“I/O Transceiver (stage II)” sub-block 610 represents the packagedependent stage of the I/O transceiver.

As will thus be appreciated, by providing IP that is pre-verified at apackage level, the level of functional abstraction is raised, thusgreatly simplifying the integration effort of IP to an SOC, andminimizing integration risk associated therewith. This in turn reducesthe time-to-market, as well as enhances the chip success rate. Bydefinition of a PLIP, high-speed connectivity IPs (e.g., a mixed signaldesign) are required to be silicon pre-verified in the same chip packagein which the IP will be used. Thus, where the IP is already suppliedwith the package level verification, the dependency of the SOC and IPfine-tuning on the silicon and packaging processes is eliminated.

While the invention has been described with reference to a preferredembodiment or embodiments, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedfor elements thereof without departing from the scope of the invention.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodiment disclosedas the best mode contemplated for carrying out this invention, but thatthe invention will include all embodiments falling within the scope ofthe appended claims.

1. A system on chip (SOC) having pre-verified, package-levelintellectual property (PLIP), the system comprising: at least oneintellectual property (IP) core formed on an integrated circuit die,said at least one IP core having external connections with respect tosaid die; a package generic unit included within said at least one IPcore, said package generic unit configured for providing externalinterface functions with respect to the SOC, wherein said packagegeneric unit is pre-verified in silicon and independent of the specificpackaging of the SOC; and a package adaptation unit included with saidat least one IP core, said package adaptation unit configured forproviding external interface functions with respect to said SOC, whereinsaid package adaptation unit is pre-verified in silicon and dependentupon the specific packaging of said SOC.
 2. The system of claim 1,wherein said package generic unit further comprises a powering and levelshifting sub-block configured to convert voltages from an internal levelused within said SOC to an input/output (I/O) signal level, saidpowering and level shifting sub-block further configured to providepackage independent functions related to internal power distributionwithin said SOC.
 3. The system of claim 1, wherein said package genericunit further comprises a custom internal interface sub-block configuredto separate SOC control signals and input/output (I/O) signals.
 4. Thesystem of claim 1, wherein said package generic unit further comprises asub-block configured to adjust a transmission line voltage to a fixedlevel in the absence of data transmitted or received thereon.
 5. Thesystem of claim 1, wherein said package generic unit further comprises afirst stage input/output (I/O) transceiver sub-block, and wherein saidpackage adaptation unit further comprises a second stage input/output(I/O) transceiver sub-block.
 6. The system of claim 1, wherein saidpackage generic unit further comprises: a powering and level shiftingsub-block configured to handle package independent power distributionand to convert voltages from an internal level used within said SOC toan input/output (I/O) signal level; a custom internal interfacesub-block configured to separate SOC control signals and I/O signals; apull-up/pull-down sub-block configured to adjust a transmission linevoltage to a fixed level in the absence of data transmitted or receivedthereon; a first stage input/output (I/O) transceiver sub-block; and athreshold and enable sub-block configured to generate control signalsused by said level shifting sub-block, said custom internal interfacesub-block, said pull-up/pull-down sub-block and said first stage I/Otransceiver sub-block.
 7. The system of claim 1, wherein said packageadaptation unit further comprises a package RCL sub-block configured formodeling resistance, capacitance and inductance values along a tracefrom a package pin to a pin on said SOC.
 8. The system of claim 1,wherein said package adaptation unit further comprises a signal landingsub-block configured for physically connecting signals between thespecific packaging of said SOC and said SOC.
 9. The system of claim 1,wherein said package adaptation unit further comprises a powering andpower/ground clamp sub-block configured for electrostatic dischargeprotection of said SOC, said powering and power/ground clamp sub-blockfurther configured to provide package dependent functions related topower distribution within said SOC.
 10. The system of claim 1, whereinsaid package adaptation unit further comprises an impedance matching andline termination sub-block configured for minimizing signal reflectionin both input and output directions.
 11. A method for generatingpreverified, package-level intellectual property (PLIP) for system onchip (SOC) devices, the method comprising: defining at least oneintellectual property (IP) core to be included in an SOC formed on anintegrated circuit die, said at least one IP core having externalconnections with respect to said die; defining a package generic unitwith said at least one IP core, said package generic unit configured forproviding external interface functions with respect to said SOC, whereinsaid package generic unit is pre-verified in silicon and independent ofthe specific packaging of said SOC; and defining a package adaptationunit with said at least one IP core, said package adaptation unitconfigured for providing external interface functions with respect tosaid SOC, wherein said package adaptation unit is pre-verified insilicon and dependent upon the specific packaging of said SOC.
 12. Themethod of claim 11, wherein said package generic unit further comprisesa powering and level shifting sub-block configured to convert voltagesfrom an internal level used within said SOC to an input/output (I/O)signal level, said powering and level shifting sub-block furtherconfigured to provide package independent functions related to internalpower distribution within said SOC.
 13. The method of claim 11, whereinsaid package generic unit further comprises a custom internal interfacesub-block configured to separate SOC control signals and input/output(I/O) signals.
 14. The method of claim 11, wherein said package genericunit further comprises a sub-block configured to adjust a transmissionline voltage to a fixed level in the absence of data transmitted orreceived thereon.
 15. The method of claim 11, wherein said packagegeneric unit further comprises a first stage input/output (I/O)transceiver sub-block, and wherein said package adaptation unit furthercomprises a second stage input/output (I/O) transceiver sub-block. 16.The method of claim 11, wherein said package generic unit furthercomprises: a powering and level shifting sub-block configured to handlepackage independent power distribution and to convert voltages from aninternal level used within said SOC to an input/output (I/O) signallevel; a custom internal interface sub-block configured to separate SOCcontrol signals and I/O signals; a pull-up/pull-down sub-blockconfigured to adjust a transmission line voltage to a fixed level in theabsence of data transmitted or received thereon; a first stageinput/output (I/O) transceiver sub-block; and a threshold and enablesub-block configured to generate control signals used by said levelshifting sub-block, said custom internal interface sub-block, saidpull-up/pull-down sub-block and said first stage I/O transceiversub-block.
 17. The method of claim 11, wherein said package adaptationunit further comprises a package RCL sub-block configured for modelingresistance, capacitance and inductance values along a trace from apackage pin to a pin on said SOC.
 18. The method of claim 11, whereinsaid package adaptation unit further comprises a signal landingsub-block configured for physically connecting signals between thespecific packaging of said SOC and said SOC.
 19. The method of claim 11,wherein said package adaptation unit further comprises a powering andpower/ground clamp sub-block configured for electrostatic dischargeprotection of said SOC, said powering and power/ground clamp sub-blockfurther configured to provide package dependent functions related topower distribution within said SOC.
 20. The method of claim 11, whereinsaid package adaptation unit further comprises an impedance matching andline termination sub-block configured for minimizing signal reflectionin both input and output directions.